The invention relates generally to the field of integrated circuit devices, and more particularly to reducing the effect of ringing and other undesirable characteristics in an input clock signal.
Many complex integrated circuit devices depend upon clear input signals (particularly unambiguous clock signals) in order to synchronize complex combinatorial logic functions and thereby generate accurate, predictable results. One common signal problem is ringingxe2x80x94voltage oscillations above and below the eventual steady-state level. Ringing is often caused by reflections on improperly terminated transmission lines on printed circuit boards. A signal that exhibits ringing retreats (undershoots or rings back) from its initial maximum-high or minimum-low level. If the signal retreats too far, the receiving circuit can read it as the wrong value. If the signal is a clock, false triggering can result. The clock signal illustrated in FIG. 1 illustrates common ringing characteristics.
One available method of avoiding the consequences of ringing on data lines is to wait for the reflections to subside before allowing the system to process new data. However, to achieve the extra delay in existing systems one must either add one or more clock cycles to each operation, or reduce the system""s clock frequency. Neither of these options is particularly desirable. Further, these methods are not applicable to ringing on clock lines.
While there are numerous schemes available to ensure that clocking signals are relatively free of irregularities, there remains a need in the art for a system and method of suppressing signal irregularities and their effects without otherwise slowing system performance.
To address the shortcomings of the available art, the present invention provides an input signal latching circuit for suppressing the effect of any ringing or other irregularity that occurs within a specified time period after an incoming voltage transition, and doing so without significantly delaying the propagation of the input transition to the intended recipient device.
The invention provides, in an integrated circuit device receiving an input signal, the input signal including sporadic irregularities during transitions between high and low signal levels, a circuit for suppressing the irregularities and forwarding an improved input signal without substantially delaying propagation of the input signal to the device. In one embodiment of the invention, the circuit comprises a delay element in electrical communication with the input signal. The delay element forwards to an output node a version of the input signal delayed by a time duration X. The circuit also includes logic means, positioned between the delay element output node and a latch, that selectively forwards either the input signal or the delayed version of the input signal to the latching element. Therefore, the latch latches the first transition of the input signal, thereby suppressing irregularities in the input signal during the time duration X after the input signal crosses a transition between a high and low signal level.